Senior Designer, Layout

The Senior Designer, Layout is mainly responsible for the creation of section level layouts. He/she will mostly work with schematic designers, block layout resources and lead layout people. His/her job is to meet schedule, design and quality requirements set by project stakeholders.

Key Qualifications:
- Extensive section (multi-hierarchical) level layout experience
- Top/Chip level layout is an advantage
- Strong fundamental knowledge in semiconductor device physics, cross-section and construction
- Strong fundamental knowledge in layout principles, IC reliability and failure mechanisms
- Proficiency in Cadence Virtuoso XL and Calibre verification tools is an advantage

Education and Experience
- BS Electronics or Electrical Engineering
- At least 4 years of relevant working experience


Additional Requirements
- Strong communications skills, both oral and written
- Able to work and effectively collaborate with a cross-functional and global team
- Strong leadership skills
- Layout experience in any of the following areas is an advantage: ADC, DAC, array-based
layout, High-Voltage Applications
- Layout experience in the following technology nodes is a plus: 0.18um, 65nm and 40nm